HBM3E vs HBM4 vs HBM4E: What Actually Changes for AI?

HBM3E, HBM4, and HBM4E aren't three competing products sitting on the same shelf. They're three stages of the same JEDEC-defined memory lineage, and as of September 2026 all three are active in the product cycle at once — just at very different stages. HBM3E is an established generation already shipping in accelerators. HBM4 is now in mass production at all three major suppliers. HBM4E remains in the customer-sampling stage.

The specs diverge more than most comparison charts suggest, too, because SK hynix, Samsung, and Micron each ship different pin speeds, capacities, and bandwidth figures under the same generation label. This piece separates the JEDEC standard baseline from what each supplier actually ships, and keeps each generation's status — sampling, mass production, or shipping — clearly labeled rather than blurred together.

If you want the underlying mechanics of what HBM is and how it differs from GDDR/DDR memory, that ground is covered in HBM Explained: Why AI GPUs Need High-Bandwidth Memory. This article assumes that background and focuses only on what changes generation to generation.

Status First: Who's Actually Shipping What

The most common mistake in generation comparisons is treating "HBM3E," "HBM4," and "HBM4E" as parallel options a buyer picks between. They're not — they're sequential, overlapping rollouts, and mixing up "sampled" with "mass production" changes what a comparison actually means.

Generation	Status as of Sept. 2026	Key dates
HBM3E	Established, shipping	SK hynix began 12-Hi (36 GB) volume production 2024-09-26
HBM4	Mass production / commercial shipment at all three suppliers	SK hynix samples 2025-03-19, development complete/mass-production-ready 2025-09-12, mass shipments began in Q2 2026; Samsung mass production from 2026-02-12; Micron high-volume production from Q1 2026
HBM4E	Sampling only — no vendor has announced mass production	Samsung samples from 2026-05-29; SK hynix samples from 2026-06-18; Micron targeting calendar-2027 volume production, no samples announced yet

None of the three suppliers has announced HBM4E mass production as of this date. Samples shipping to customers is a real milestone, but it isn't the same thing as volume production, and the two shouldn't be conflated when reading vendor announcements.

What the JEDEC Standard Itself Changed

JEDEC published the HBM4 standard as JESD270-4 in April 2025. The headline structural change is that the interface per stack doubles from HBM3E's 1,024-bit width to 2,048-bit, split across 32 independent channels instead of 16. That wider bus is a major reason total bandwidth roughly doubles even before accounting for any pin-speed increase.

	HBM3E	HBM4 (JESD270-4)
Interface width per stack	1,024-bit	2,048-bit
Independent channels	16	32
Standard pin-speed ceiling	—	up to 8 Gb/s
Bandwidth at that ceiling	—	up to ~2 TB/s per stack
Stack configurations	up to 12-Hi in current shipping parts	4-Hi, 8-Hi, 12-Hi, 16-Hi; 24 Gb or 32 Gb per die; up to 64 GB at 16-Hi

Secondary reporting isn't fully consistent on whether 8 Gb/s is a hard JEDEC ceiling or a reference figure — one uncorroborated aggregator claimed a 6.4–12.8 Gb/s range, but the two outlets independently reporting on JEDEC's own release both state "up to 8 Gb/s," so that's the baseline used here. In practice it matters less than it sounds: the vendor HBM4 products listed below already advertise pin speeds above 8 Gb/s, as the next section shows.

What Each Supplier Actually Ships in HBM4

The JEDEC standard sets a floor, not a fixed spec. SK hynix, Samsung, and Micron each ship materially different pin speeds, capacities, and bandwidth under the "HBM4" label, so a single flattened "HBM4 = X TB/s" number doesn't represent any of them accurately.

Vendor	Status	Capacity	Pin speed	Per-stack bandwidth	Process / packaging notes
SK hynix	Mass shipments began in Q2 2026	36 GB (12-Hi)	>10 Gbps (per the Sept. 2025 release)	"more than 2 TB/s" (per the March 2025 release)	1bnm (5th-gen 10nm-class) DRAM; logic foundry not disclosed
Samsung	Mass production from 2026-02-12	24–36 GB (12-Hi); up to 48 GB (16-Hi)	11.7 Gbps sustained, up to 13 Gbps	up to 3.3 TB/s at the 13 Gbps ceiling	Samsung Foundry 4nm logic + 1c (6th-gen 10nm-class) DRAM
Micron	High-volume production from Q1 2026	36 GB (12-Hi); 48 GB 16-Hi samples shipped, not yet volume production	>11 Gb/s	>2.8 TB/s — Micron states this as 2.3× HBM3E bandwidth	not disclosed

Official vendor sources: SK hynix Q2 2026 results · Samsung HBM4 commercial shipment · Micron HBM4 volume production.

SK hynix's own two 2025 releases don't reduce to one clean spec line either: the March announcement gave capacity and an approximate bandwidth figure without a pin speed, while the September announcement gave a pin-speed floor and I/O count without restating bandwidth. That's most likely the part maturing between sample shipment and development-complete milestones, but it's worth citing each figure to its own release date rather than blending them into a single number.

On base-die manufacturing, Samsung directly confirms its 4nm logic base die in its own release. SK hynix's process is less settled in public reporting: trade press describes a reported shift toward TSMC's 12nm-class logic process for the base die supplied on current NVIDIA parts, a change from SK hynix's earlier in-house base-die production, and Micron's process node hasn't been disclosed at all. Treat the SK hynix and Micron figures as single-source, reported rather than vendor-confirmed.

HBM4E: Sampling at Two Vendors, Not Yet in Mass Production

HBM4E is the generation most likely to get overstated. Samsung and SK hynix have both shipped samples, which is real progress — but "samples shipped" and "in development" are also both true statements at once, and neither is "mass production."

Vendor	Status	Capacity	Pin speed	Per-stack bandwidth	Process / packaging notes
Samsung	Samples from 2026-05-29	48 GB (12-Hi); 8-Hi and 16-Hi variants planned	14 Gbps stable; scalable up to 16 Gbps	"up to 3.6 TB/s" (see note below)	Samsung Foundry 4nm logic base die + 1c DRAM
SK hynix	Samples from 2026-06-18	48 GB (12-Hi)	up to 16 Gbps	~4.1 TB/s theoretical at 16 Gbps (calculated from the 2,048-bit interface)	Advanced MR-MUF packaging retained
Micron	No samples announced; targeting calendar-2027 volume production	—	—	—	1-gamma DRAM technology

Official vendor sources: Samsung HBM4E samples · SK hynix HBM4E samples.

Micron is later in this HBM4E rollout than Samsung and SK hynix — a different position than in plain HBM4, where it's in volume production alongside both vendors. TrendForce separately projects HBM4E reaching roughly 40% of total HBM demand in 2027, with Samsung and SK hynix both reportedly targeting 1H 2026 for HBM4E development completion; that's TrendForce's market estimate, not a vendor claim, and it's cited here as such.

A quick math note on Samsung's HBM4E numbers, since they don't fully reconcile on their own: Samsung states a 14 Gbps stable pin speed that is scalable up to 16 Gbps, and separately states "up to 3.6 TB/s" per stack. Multiplying 14 Gb/s by the 2,048-bit interface works out to roughly 3.58 TB/s — consistent with the quoted 3.6 TB/s. Multiplying 16 Gb/s by the same interface works out to roughly 4.1 TB/s, not 3.6 TB/s. Samsung's own release doesn't explicitly connect the two figures, so the more accurate reading is that 3.6 TB/s corresponds to the 14 Gbps stable speed, not the 16 Gbps figure — not that 16 Gbps yields 3.6 TB/s.

What Stayed the Same: Packaging

One thing that didn't change is worth stating explicitly, since it's easy to assume otherwise: HBM4 did not bring a shift to hybrid bonding. JEDEC relaxed the HBM4 package-height limit to 775 μm, which lets both SK hynix's Advanced MR-MUF approach and Samsung's TC-NCF approach qualify for 16-Hi stacks. SK hynix is reportedly retaining MR-MUF for HBM4 (and continues to use it in HBM4E samples per its own release), while evaluating fluxless bonding as an interim step. Per TrendForce's reporting, hybrid bonding is more likely to become necessary at HBM5-class stack heights above 20 layers, not for HBM4 or HBM4E.

What This Means for AI Accelerators Right Now

For anyone specifying or evaluating AI accelerator memory today, the practical picture is an unusual three-way overlap rather than a clean succession. HBM3E is the proven, already-shipping choice. HBM4 is now broadly available across all three major suppliers, but "HBM4" alone doesn't specify enough — vendor, capacity, and pin speed all need to be stated together, since SK hynix, Samsung, and Micron ship meaningfully different numbers under the same standard. HBM4E exists only in sample form, aimed at platforms that won't reach volume until roughly 2027 on current vendor and analyst timelines.

None of this article's numbers should be read as a verdict on which supplier is ahead — that's a separate question this article deliberately leaves open for a dedicated comparison. AI NodeLab's earlier piece, The AI Memory Wall Explained: Why Faster GPUs Are No Longer Enough, covers why this generational race matters in the first place, and a future piece will look specifically at how Samsung, SK hynix, and Micron compare on HBM market position.