Hybrid Bonding vs. Microbumps: What Changes Inside an HBM Stack?

A taller HBM stack does not tell you how its dies are bonded. SK hynix’s CES 2025 announcement described 16-layer HBM3E samples using Advanced MR-MUF—not hybrid bonding. That is a useful starting point for a technology often presented as an automatic consequence of adding more layers.

Hybrid bonding changes the interface between dies: it replaces protruding solder microbumps with direct copper connections and a bond between the surrounding insulating surfaces. It can support finer connections and thinner interfaces. Whether that becomes a useful HBM product still depends on the design and manufacturing process.

The historical example comes from SK hynix’s January 2025 CES release. It describes samples to be exhibited, not proof of current commercial shipments. The point is narrower: layer count alone does not identify the bonding method.

What is actually being joined?

Zoom in on the boundary between two stacked dies. In a microbump-based connection, small solder-based joints bridge the facing electrical contacts. Material around the joints supports and protects the assembly.

In hybrid bonding, copper pads are embedded in insulating surfaces. The facing copper pads form electrical connections, while the surrounding dielectric surfaces bond to one another. A dielectric is an electrical insulator. “Hybrid” refers to those two bonding mechanisms—not a mixture of solder bumps and direct copper bonding.

The interface therefore changes more substantially than the size of the bump. Imec’s process explanation describes the copper-to-copper and dielectric-to-dielectric bonds, including the surface preparation needed to form them.

At the die interface	Microbump-based connection	Hybrid bonding
Electrical path	Solder-based joints connect facing contacts.	Facing copper pads bond directly.
Surrounding material	Underfill or film supports the space around the joints.	Prepared dielectric surfaces bond across the interface.
Vertical separation	Protruding joints contribute to the gap between dies.	No protruding solder microbumps at the bonded interface.
Manufacturing emphasis	Control joint formation and the surrounding protective material.	Control surface flatness, cleanliness and pad alignment.

This is a comparison of interfaces, not a ranking of finished memory products. Imec describes bonding choices as tradeoffs involving pitch, cost and compatibility.

Finer pitch and a thinner stack are different benefits

Pitch measures the spacing between neighboring connections across a surface. The gap between dies is a vertical dimension. A small pitch number does not tell you how thick a memory die is, and neither measurement is the DRAM manufacturing node.

Hybrid bonding can reduce the space occupied by the inter-die connection while allowing contacts to be packed more closely. That creates design room. It does not, by itself, specify the finished stack’s capacity or bandwidth.

Thickness and heat are both concerns in SK hynix’s Korean-language HBM technical discussion. Removing a bump-based interface can help the stack design, but it does not make the rest of the thermal problem disappear. A claim about lower interface resistance is not automatically a claim about a cooler accelerator under every workload.

Nor does changing the bond turn the entire package into a different architecture. A TSV carries a connection through silicon; a bond joins facing surfaces. Removing microbumps at an interface does not, on its own, establish that TSVs have disappeared or that memory now sits above the GPU. The CoWoS explainer covers the separate task of integrating HBM with logic at the package level.

The difficult part moves to the surface

A direct bond needs its facing surfaces to meet reliably. A particle, uneven surface or misaligned pad can interfere with that contact. Imec identifies chemical-mechanical polishing, or CMP, as a demanding preparation step: it controls surface flatness and how far copper pads sit below the surrounding dielectric before bonding.

The challenge continues after preparation. In its die-to-wafer research, imec explains the need to preserve clean surfaces while separating dies from the wafer and placing them for bonding. A process that achieves a fine pitch must also survive those handling steps.

This is where wafer-to-wafer and die-to-wafer results need to be kept separate. Wafer-to-wafer bonding joins wafers. Die-to-wafer bonding places individual dies onto a wafer, allowing selection of dies that have passed testing and integration of unequal die sizes. That flexibility brings placement and handling demands of its own.

Wafer-to-wafer bonding joins full wafers, while die-to-wafer bonding places selected individual dies onto a wafer. Schematic, not to scale; the repeated examples do not represent a performance ranking. Process reference: imec.

A pitch record from one flow is not a drop-in specification for the other. Comparing them without the assembly method is like comparing production results without saying what was produced.

Read the evidence before the adoption headline

In May 2026, imec and EV Group reported 200 nm copper-pad pitch in wafer-to-wafer hybrid bonding on a test vehicle with routable interconnects. That is a research result. It is not a specification for a commercially shipped HBM stack.

The same discipline helps when reading memory vendors’ announcements. These selected disclosures establish different kinds of progress; they are not interchangeable milestones or a complete survey of HBM adoption.

Public evidence	What it establishes	What it does not establish
Imec/EVG, May 2026: 200 nm wafer-to-wafer test vehicle	A demonstrated research process in the reported setup.	A commercial HBM product using that pitch.
SK hynix, January 2025: 16-layer HBM3E samples described for CES	A dated sample announcement explicitly using Advanced MR-MUF.	Hybrid bonding inferred from the layer count, or current shipment volume.
Samsung’s HBM3E FAQ: preparing HCB adoption	A stated preparation for Hybrid Copper Bonding.	A named product’s completed qualification or shipment date.
Samsung, FMS 2026: zHBM architecture proposal	A disclosed direction combining memory-over-processor integration with HCB and multi-wafer bonding.	That ordinary HBM4 products already use that architecture.

Samsung’s Korean product FAQ uses preparation language for HCB. Its separate FMS 2026 discussion of zHBM describes a proposed memory-over-processor architecture. Keeping those statements separate avoids turning a future direction into a present product claim.

What this means for the Korean HBM story

MR-MUF and TC NCF are names for assembly approaches, not competing memory standards. SK hynix’s MR-MUF involves reflow and molded underfill; Samsung’s TC NCF uses thermal compression and a non-conductive film. The insulating material is not the electrical signal path. Hybrid bonding changes how the facing surfaces and electrical contacts are joined.

There is also a reason to read a technical essay differently from a product announcement. An August 2026 guest technical note hosted by SK hynix describes hybrid bonding as necessary for 16-layer-and-higher HBM. Read as a blanket rule, that conflicts with the company’s earlier description of a 16-layer MR-MUF sample. The specific sample evidence is enough to reject “16 layers means hybrid bonding”; it does not settle which process a future product will use.

For readers following Korean memory companies, the useful question is not simply who mentions hybrid bonding first. It is whether the chosen process meets the particular product’s electrical, thermal and manufacturing requirements. Continuing to improve a bump-based process is not, by itself, evidence of falling behind. Announcing a direct-bonding result is not, by itself, evidence of a commercial lead.

If tighter connection spacing or stack-height constraints make hybrid bonding more valuable in a particular design, adoption could become more attractive. The timing still needs product-level evidence. No single layer count or laboratory pitch supplies that evidence on its own.

Before treating the next announcement as an HBM adoption milestone, look for the named product, the exact interface being bonded, and the stage demonstrated: test structure, sample, qualification or shipment. Then ask whether the reported benefits survive the relevant thermal, reliability and manufacturing conditions. That is the difference between a promising connection and a memory product a customer can deploy.