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HBM4 is not only a faster stack of DRAM. Its base die—the logic layer beneath the memory dies—is becoming a strategic part of the product. Samsung is already shipping HBM4 built with a 4nm logic base die. SK hynix has begun mass shipments and says its HBM4 base die uses TSMC advanced logic. Micron is shipping HBM4 for NVIDIA Vera Rubin, although its cited release does not identify the base-die process.
The overlooked distinction is that a more capable base die is not automatically the same thing as fully customized HBM. Standard HBM4, vendor-specific implementation, and customer-specific Custom HBM are three different levels. Mixing them leads to misleading comparisons.
Last fact-check: September 10, 2026.
What Is the Base Die in an HBM Stack?
An HBM package places several DRAM dies above a base die and connects the stack vertically through through-silicon vias, or TSVs. The base die sits at the bottom of that stack, between the memory layers and the package-level connection to an AI accelerator.
If you need the broader architecture first, see HBM Explained: How AI GPU Memory Works.
The DRAM dies provide memory capacity. The base die provides the logic-facing foundation through which the stack's wide interface is implemented. It participates in the electrical, signaling, power-delivery, and test structure needed to connect thousands of data paths across the stack and package.
That does not mean HBM4 has moved an accelerator's entire memory controller into the memory stack. Nor does it mean every HBM4 base die contains customer-specific compute. Those are separate architectural choices. The safest description is narrower: HBM4 gives the logic layer more strategic importance and more room for differentiation.
Why HBM4 Makes the Base Die More Important
HBM4 doubles the external interface from 1,024 to 2,048 I/O pins. This is the architectural reason bandwidth rises even without an equally dramatic increase in per-pin speed.
The theoretical relationship is simple:
Pin rate × interface width ÷ 8 = bandwidth
| Pin rate | Interface width | Theoretical bandwidth per stack |
|---|---|---|
| 8 Gbps | 2,048 bits | 2.048 TB/s |
| 11.7 Gbps | 2,048 bits | 2.9952 TB/s |
| 13 Gbps | 2,048 bits | 3.328 TB/s |
These are AI NodeLab calculations using decimal units, not measured workload throughput. Samsung reports a maximum of 3.3 TB/s for its implementation, which aligns with the rounded 13 Gbps calculation. For the larger generational comparison, see HBM3E vs HBM4 vs HBM4E.
Doubling the interface also doubles the physical problem. More connections must be routed, powered, tested, and kept within tight signal and thermal limits. That makes the relationship among the DRAM process, base-die logic process, interposer, accelerator, and package harder to treat as a collection of independent parts.
This is why HBM4 vendor announcements now mention logic process nodes and co-optimization strategies—not just DRAM generations and stack heights.
Three Levels That Should Not Be Confused
The easiest way to understand HBM4 customization is to separate three layers of meaning.
1. The HBM4 Standard
The standard defines a common interface and operating framework. Vendor announcements describe 2,048 I/O pins and cite 8 Gbps as the JEDEC operating baseline. This common foundation is what allows the industry to call different products “HBM4.”
But a standard does not make every physical implementation identical. Companies can choose different DRAM nodes, logic nodes, bonding methods, package strategies, and validated speed targets while still building to the same generation of HBM.
2. Vendor-Specific Base-Die Implementation
This is already visible in commercial HBM4.
Samsung says its shipping product combines sixth-generation 10nm-class DRAM, known as 1c, with a 4nm logic base die. The company emphasizes in-house Design Technology Co-Optimization between its Memory and Foundry businesses.
SK hynix says it is adopting TSMC's advanced logic processes for the base die starting with HBM4. Its strategy combines SK hynix memory design and packaging with an external advanced-logic foundry ecosystem.
Both approaches use advanced logic, but the supply chain and co-design structure are different. One is vertically integrated within Samsung; the other is built around the SK hynix–TSMC partnership. A process-node label alone cannot tell us which approach has better yield, power, or customer fit. Those outcomes require product-level evidence.
3. Customer-Specific Custom HBM
Custom HBM goes further. It implies that the memory product is shaped around a particular customer's accelerator or workload requirements, rather than offered only as a standardized configuration.
SK hynix has publicly said it plans to move beyond standardized HBM and provide Custom HBM tailored to customer requirements. Samsung says samples of its Custom HBM are scheduled to reach customers in 2027.
Those statements are roadmaps. They should not be rewritten as proof that all HBM4 shipping in 2026 already contains bespoke customer logic. Today's vendor-specific base dies are the foundation for more customization, not evidence that the transition is complete.
Samsung vs SK hynix vs Micron: What Is Confirmed?
The table below normalizes company disclosures as of September 10, 2026. It deliberately separates current product status from future customization plans.
| Vendor | Disclosed base-die approach | Verified HBM4 status | Named platform or customer | Custom-HBM status |
|---|---|---|---|---|
| Samsung | 4nm logic base die; in-house Memory–Foundry co-optimization | Began mass production and commercial shipments in February 2026 | MOU covering primary HBM4 supply for AMD Instinct MI455X | Customer samples planned for 2027 |
| SK hynix | TSMC advanced logic process for the HBM4 base die | Began mass shipments in Q2 2026; production ramp planned for H2 | No customer named in the cited Q2 shipment disclosure | Public roadmap for customer-tailored Custom HBM |
| Micron | Base-die foundry and process not identified in the cited release | Began volume shipment of 36GB 12-high HBM4 in Q1 2026 | NVIDIA Vera Rubin | No comparable Custom-HBM timeline in the cited release |
“Not identified” is not the same as “does not exist.” It means the public source used for this comparison does not support a more specific statement. That distinction matters in an industry where customer programs and manufacturing details are often disclosed at different times.
For a wider company comparison covering HBM roadmaps and product status, read Samsung vs SK hynix vs Micron HBM in 2026.
What the Base Die Changes for AI Accelerators
HBM Becomes a Co-Design Problem
With earlier HBM generations, readers could get surprisingly far by comparing capacity, stack height, and bandwidth. HBM4 makes that shortcut less reliable.
The 2,048-bit interface must work across the base die, stack, interposer, package, and accelerator. A change in one layer can affect power delivery, signal integrity, thermals, physical routing, or validation elsewhere. The practical unit of optimization is moving closer to the complete accelerator package.
This does not make standardized specifications irrelevant. It means the standard is the starting boundary, not the full product description.
Foundry Strategy Becomes Part of Memory Strategy
Samsung's 4nm base die highlights the advantage it is trying to extract from owning both memory and foundry capabilities. SK hynix's TSMC partnership highlights a different advantage: access to a leading logic-process and packaging ecosystem while SK hynix focuses on memory and HBM integration.
Neither structure guarantees the better product. The useful conclusion is that foundry choice is now a visible HBM variable. Analysts comparing only the DRAM node are leaving out part of the design.
Micron's current HBM4 announcement is a good reminder not to fill disclosure gaps with assumptions. Its volume-shipment and Vera Rubin claims are confirmed. The base-die process and foundry are not specified in that release, so a like-for-like manufacturing comparison remains incomplete.
Customization Can Increase Differentiation—and Validation Work
A customer-specific base die could allow the memory interface and supporting logic to be optimized more closely for an accelerator architecture. That is the opportunity behind Custom HBM.
The tradeoff is deeper coordination. More customer-specific design choices imply more co-development, verification, and production dependencies than an off-the-shelf comparison table can show. This is an inference from the vendors' stated co-design direction, not a disclosed universal rule for every HBM4 contract.
It also suggests that switching suppliers may become more complicated as customization deepens. Again, this should be treated as a strategic implication, not proof that HBM4 is technically single-sourced by definition.
Why This Matters for the AI Memory Wall
The AI memory wall is not solved by peak compute alone. Accelerators need enough memory bandwidth and capacity to keep expensive compute units fed with data.
HBM4 attacks the bandwidth side with a 2,048-bit interface. The base die matters because that interface must be turned into a manufacturable, power-efficient connection between the DRAM stack and the accelerator package.
Custom logic may eventually help vendors optimize that boundary for specific systems or workloads. But it cannot erase every bottleneck. Model architecture, memory capacity, interconnect bandwidth, software behavior, thermals, and power limits still shape realized performance. A 3.3 TB/s peak specification is not a promise that an application will sustain 3.3 TB/s.
How to Evaluate an HBM4 Announcement
When a company announces HBM4 or Custom HBM, check these five questions before accepting the headline:
- What is the product status? Development, sampling, qualification, mass production, and commercial shipment are different milestones.
- Is the number standard, measured, or calculated? A theoretical interface rate is not the same as application throughput.
- What has been disclosed about the base die? Look for the logic process, design owner, foundry relationship, and packaging approach.
- What does “custom” modify? A vendor-specific base die is not automatically a customer-specific design.
- Is a customer or platform named? A signed MOU, a designed-for statement, and confirmed volume deployment do not carry identical weight.
This framework is more useful than ranking vendors by one headline speed. HBM4 competition now spans memory, logic, packaging, and customer co-design—and the public evidence for each layer arrives on a different timeline.
The Practical Takeaway
The HBM4 base die should be read as a strategic boundary, not as a miniature AI accelerator hidden under every memory stack.
For current products, compare the disclosed logic process, integration model, shipment status, and validated bandwidth. For Custom HBM, demand a second set of evidence: what is customized, for whom, and whether it is a roadmap, a sample, or a shipping product.
Samsung, SK hynix, and Micron have all reached HBM4 production or shipment milestones. Their public disclosures are not equally detailed, and their base-die strategies are not directly interchangeable. That asymmetry is not a nuisance to be smoothed over. It is the most important part of the comparison.
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